1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and particularly to an alignment technique used for photolithography steps.
2. Description of the Related Art
Photolithography techniques are utilized in manufacturing semiconductor integration circuit devices. In the techniques of this kind, a selected portion of a photo-resist film is subjected to light exposure to form a certain pattern. The photo-resist film with the certain pattern thus formed is used as a barrier wall (mask) in etching an insulative film or conductive film, or a barrier wall (mask) in ion-implanting an impurity. When light exposure is performed on the photo-resist film, a photo mask is used. The photo mask has a certain pattern drawn thereon, which is to be transferred onto the photo-resist film. When the transfer is performed, it is important to accurately align the photo mask with a predetermined position. For this purpose, an alignment mark is formed on a wafer or chip. For example, a light exposure apparatus detects the alignment mark, and thereby aligns the photo mask with a predetermined position. Alignment marks of this kind are disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 7-147221 (Patent Document 1). Incidentally, hereinafter, a processing step utilizing a photolithography technique is referred to as a PEP or PEP step, as needed.
Next, manufacture of a Flash EEPROM of the NAND type will be explained as a specific example of manufacture of a semiconductor integration circuit device. In the case of a Flash EEPROM of the NAND type, well formation steps and channel ion implantation steps (the latter steps are used each for introducing an impurity for adjusting a threshold voltage) are performed before a floating gate formation step. This is disclosed in, e.g., Jpn. Pat. Appln. KOKAI Publication No. 2002-9173 (Patent Document 2). Thus, the well formation steps are performed inevitably before a step of forming a device isolation area to define active areas (which will be referred to as an STI (shallow trench isolation) step for example, hereinafter). In the well formation steps, different impurities are implanted into respective predetermined portions, as required. Accordingly, PEPs are respectively performed in a plurality of steps. Since the PEPs are performed like this, it is necessary to prevent the layers formed by the respective PEPs (each of which will be referred to as a PEP layer) from causing misalignment with each other. For this purpose, a step of forming only an alignment mark is performed before the well formation steps. This alignment mark is sometimes called a ZL mark, and the step of forming only an alignment mark is sometimes abbreviated as a ZL step.
Since each well formation step is arranged to merely implant an impurity into a semiconductor substrate, it leaves no clear mark on the substrate surface. Accordingly, an alignment mark (ZL mark) is formed to be utilized in subsequent PEP steps. For example, the ZL step is performed as a first PEP step to form only an alignment mark on a substrate surface, such as a wafer surface or chip surface. Then, each of the PEPs for the well formation steps is performed while using a photo mask aligned with the alignment mark thus formed. The PEP for the STI step is also performed while using a photo mask aligned with the alignment mark thus formed.
However, this manufacturing technique performs a PEP step only for formation of an alignment mark. The alignment mark has nothing to do with the device operation. Further, the PEP step is relatively expensive among the processing steps for an integration circuit. Thus, the PEP step only for formation of an alignment mark increases the manufacturing cost.
Further, each of the PEPs for the well formation steps is performed while using a photo mask aligned with the alignment mark. Accordingly, the alignment between the wells is indirect alignment. The PEP for the STI step is also performed in the same manner, and thus the alignment between the wells and STI is also indirect alignment. This problem makes it difficult to decrease the size of chips.